View S2061_2098297.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 serial backplane transceiver S2061 february 2, 1999 / revision c bicmos pecl clock generator ? device specification serial backplane transceiver S2061 features ? transmitter incorporates phase-locked loop (pll) providing clock synthesis from low-speed reference ? receiver pll configured for clock and data recovery ? 1.0 C 1.25 gbps operation ? 8-bit parallel ttl compatible interface ? 1.6w typical power dissipation ? +3.3v power supply ? low-jitter serial pecl compatible interface ? lock detect ? local loopback ? 64 pqfp/tep package ? framing performed by receiver ? continuous downstream clocking from receiver ? drives 30m of twinax cable directly applications high-speed data communications ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes ? raid drives ? mass storage devices general description the S2061 transmitter and receiver chip is designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces. the chip runs at data rates from 1.0 to 1.25 gbps with associated 10-bit data word. the chip performs parallel-to-serial and serial-to-par- allel conversion, 8b/10b coding, and framing for block-encoded data. the transmitters on-chip pll synthesizes the high-speed clock from a low-speed reference. the receivers on-chip pll synchronizes directly to incoming digital signal to receive the data stream. the transmitter and receiver each support differential pecl-compatible i/o for fiber optic com- ponent interfaces, to minimize crosstalk and maximize data integrity. local loopback mode is provided for system diagnostics. figure 1 shows a typical configuration incorporating the chip, which is compatible with amccs crosspoint switch products. figure 1. system block diagram crosspoint switch s2016(16x16) s2025(32x32) s2028(32x32) mac mac 1000 gbe oc-3 oc-12 fibre channel 0 n 0 n S2061 mac mac S2061 S2061 S2061 1000 gbe oc-3 oc-12 fibre channel 1000 gbe oc-3 oc-12 fibre channel 1000 gbe oc-3 oc-12 fibre channel
2 serial backplane transceiver S2061 february 2, 1999 / revision c figure 2. functional block diagram txtestn tx [0:7] 10 8 pll clock multiplier f 0 = f 1 x 10 shift register txp txn dq pll clock recovery 2:1 d 8 d bitclk q com_det detect logic control logic rxp tbc rxn tp tn ewrap en_cdet rx[0:7] rbc1 rbc0 shift register input latch 8b10b encoder 2 tk [0,1] frame kgen wordclk lockdet 10 8 8b10b decoder kflag byterr rk[0,1] sdttl sdpecl fp S2061 overview the S2061 transceiver performs encoding/decoding parallel-to-serial and serial-to-parallel conversion and framing functions to implement a serial backplane interface. operation of the S2061 chip is straightfor- ward, as depicted in figure 2. the sequence of operations is as follows: transmitter 1. 8-bit parallel input 2. 8b/10b encoding 3. parallel-to-serial conversion 4. serial output receiver 1. clock and data recovery from serial input 2. serial-to-parallel conversion 3. frame detection 4. 10b/8b decoding 5. 8-bit parallel output internal clocking and control functions are transparent to the user. details of data timing can be seen in figures 6, 7, 8. a lock detect feature is provided for the receive pll. the lockdet output indicates that the pll is locked to the data stream. loopback modes local loopback mode is supported by the chip. local loopback provides capability for performing offline test- ing of the interface to ensure the integrity of the serial channel before enabling the transmission medium. it also allows for system diagnostics. (see the section other operating modes.)
3 serial backplane transceiver S2061 february 2, 1999 / revision c S2061 transmitter description the S2061 accepts 8-bit parallel input data, performs 8-bit to 10-bit conversion, and serializes the data for transmission over copper or fiber optic media. the transmitter can operate in the range of 1.0 ghz to 1.25 ghz, determined by the tbc frequency. data input data is input to the S2061 as an 8-bit lvttl (5v tolerant) word. data is latched into an input register on the rising edge of the input reference clock. the 8- bit data is 8b/10b coded, and the resultant 10-bit word is passed to a shift register where it is con- verted to serial data. parallel/serial conversion the parallel-to-serial converter takes 10-bit wide data from the 8b/10b converter and converts it into a se- rial bit stream. data is clocked into the serial output shift register at a rate that is synchronous to the clock synthesis unit serial clock. the shift register is clocked by the internally generated bit clock (10x the tbc input frequency). transmit byte clock the transmit byte clock (tbc) input must be sup- plied from a clock source with 100 ppm variation. the internal serial clock is frequency locked to tbc. to set transmitter operating rate (in the range of 1.0 ghz to 1.25 ghz), the tbc input frequency must be selected at 1/10 of the desired operating rate (100 mhz to 125 mhz). 8b/10b coding the 8b/10b transmission code includes serial encoding and decoding rules, special characters and error con- trol. information is encoded, 8 bits at a time, into a 10-bit transmission character. the characters defined by this code ensure that the short run lengths and enough tran- sitions are present in the serial bit stream to make clock recovery possible at the receiver. the encoding also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmis- sion and reception of data. refer to reference 1 for a complete description of the transmission code. the 8b/10b transmission code includes d-characters, used for data transmission, and k-characters, used for control or protocol functions. each d-character and k-character has a positive and a negative parity version. the parity of each codeword is selected by the encoder to control the running disparity of the data stream. in addition to the 8-bit data input, there are four con- trol inputs which are used to produce k characters: frame, tk0, tk1, and kgen. table 1 shows char- acter generation based on input states. k-character generation is controlled using the kgen input. when kgen is asserted, the data on the paral- lel input is mapped into the corresponding control character. the parity of the k-character is selected to minimize running disparity in the serial data stream. table 2 lists the k-characters supported by the S2061 and identifies the mapping of the tx[0:7] bits to each character. figure 3 shows functional waveforms of the S2061. 1. a.x. widner and p.a. franaszek, a byte-oriented dc balanced (0,4) 8b/10b transmission code, ibm research report rc9391, may 1982. e m a r f1 k t0 k tn e g k] 0 : 7 [ x te t a t s 1000x . d e t a r e n e g y t i r a p s i d g n i n n u r 5 . 8 2 k 0001 k r e t c a r a h c e u l a v n o e u l a v d e t a r e n e g y t i r a p s i d g n i n n u r f o r e t c a r a h c k . ] 7 : 0 [ d 0011x . d e t a r e n e g y t i r a p s i d g n i n n u r f o 1 . 8 2 k 0101x . d e t a r e n e g y t i r a p s i d g n i n n u r f o 3 . 8 2 k 0111x . d e t a r e n e g y t i r a p s i d g n i n n u r f o 7 . 8 2 k 0xx0 a t a d. d e t a r e n e g r e t c a r a h c d table 1. character generation
4 serial backplane transceiver S2061 february 2, 1999 / revision c figure 3. functional waveform (1250 and 1062.5 mbit/sec) refclk fp rbc1 rbc0 byte 1 00 k value byte 2 byte n rx[7:0] tx[7:0] tk1 k28.5 byte 1 k value byte 2 k28.1 byte n k28.5 k28.5 byte 1 k value byte 2 k28.1 byte n k28.5 serialdata frame kgen 0 0 01 tk0 rk0 rk1 byte_error kflag 0 0 000 0 0 0 0 0 0 010 0 0 k r e t c a r a h c ] 7 : 0 [ x tn e g k + d r t n e r r u c- d r t n e r r u c s t n e m m o c j h g f i e d c b aj h g f i e d c b a 0 . 8 2 k 1 . 8 2 k 2 . 8 2 k 3 . 8 2 k 4 . 8 2 k 5 . 8 2 k 6 . 8 2 k 7 . 8 2 k 7 . 3 2 k 5 . 7 2 k 7 . 9 2 k 7 . 0 3 k 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 r e t c a r a h c c n y s table 2. k character generation e t y b a t a d ] 9 : 0 [ x r r o ] 9 : 0 [ x t 0123456789 n o i t a t n e s e r p e r c i r e m u n a h p l a b 0 1 / b 8 abcdei fghj table 3. 8b/10b alphabetic representation
5 serial backplane transceiver S2061 february 2, 1999 / revision c receiver description the receiver is designed to implement a serial backplane receiver function through the physical layer. a block diagram showing the basic function is pro- vided in figure 2. the receiver accepts serial encoded data from a fiber optic or coaxial interface. clock recovery is performed on-chip, with the output data presented as 8-bit paral- lel data. whenever a signal is present, the receiver attempts to achieve synchronization on both bit and transmission- word boundaries of the received encoded bit stream. when bit synchronization is achieved, it is indicated by the lockdet signal. word synchronization is achieved by monitoring the incoming serial data stream for the comma character with negative disparity (0011111xxx). all k28.5 characters, with the correct byte alignment, of either disparity will be indicated by fp. additional k characters are also decoded per table 4. when word synchronization is achieved, the receiver provides the valid decoded data on its parallel outputs. decoder the decoder accepts a serial bit stream, does serial to byte-wide parallel conversion, and performs the 10b/8b decoding function. the framer recognizes the negative disparity comma to correctly frame the data. byte synchronization and framing the receiver section performs byte synchronization on the incoming data stream. byte synchronization is performed on only the negative disparity fibre chan- nel comma character (0011111xxx). thus, in order to ensure byte synchronization, it is necessary to send two comma characters in a row to ensure that one of them is negative disparity. the fp signal will be ac- tive whenever a k28.5 character of either disparity is detected. this allows the frame input of the trans- mitter and the fp output on the receiver to be used to envelope the data packet. recovered clock frequency is determined to be within approximately 300 ppm and the run length check indi- cates valid data, the pll will be declared in lock and the lock detect output will go active. in any transfer of pll control from the serial data to the reference clock, the rbc1/0 output remains phase continuous and glitch free assuring the integrity of down- stream clocking. reference clock input the reference clock input must be supplied with a crystal clock source with 100 ppm tolerance. other operating modes loopback when local loopback is enabled, serial data from the transmitter is internally routed to the receiver, where the clock is extracted and the data is deserialized. the parallel data is then sent to the subsystem for verifica- tion. this loopback mode provides the capability to perform offline testing of the interface to guarantee the integrity of the serial channel before enabling the trans- mission medium. it also allows system diagnostics. operating frequency range the S2061 is optimized for operation at 1250 and 1062 mbit/s. operation at other rates is possible if the rate falls between the nominal rates. tbc must be selected to be within 100 ppm of the desired byte or word clock rate. lock detect the s 2061 contains a lock detect circuit which monitors the integrity of the serial data inputs. if the received serial data fails the run length or frequency test, the pll will be forced to lock to the local reference clock. this will maintain the correct frequency of the rbc1/0 out- put under loss of signal or loss of lock conditions. if the serial data inputs have a run length of 80 bit times with no transitions, the pll will be declared out of lock. in addition, if the recovered clock frequency deviates from the local reference clock frequency by more than ap- proximately 600 ppm, the pll will also be declared out of lock. the lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. if the p f1 k r0 k rg a l f ke t a t s 100 1 . d e t c e t e d 5 . 8 2 k 000 1 . ] 7 : 0 [ x t n o e u l a v , d e t c e t e d r e t c a r a h c k 001 1 . d e t c e t e d 1 . 8 2 k 010 1 . d e t c e t e d 3 . 8 2 k 011 1 . d e t c e t e d 7 . 8 2 k 000 0 . r e t c a r a h c d table 4. character detection 1 1. k characters are detected with either positive or negative disparity.
6 serial backplane transceiver S2061 february 2, 1999 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 x r 6 x r 5 x r 4 x r 3 x r 2 x r 1 x r 0 x r l t to3 1 1 1 0 1 9 8 6 5 4 e h t n o d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d e v i e c e r . d e v i e c e r t i b t s r i f e h t s i 0 x r . 1 c b r d n a 0 c b r f o e g d e g n i s i r 1 c b r 0 c b r l t t . f f i do9 1 8 1 0 c b r f o e g d e g n i s i r e h t n o d i l a v s i a t a d l e l l a r a p . k c o l c e v i e c e r s i d r o w c n y s a r e t f a . ) 8 e r u g i f n i m a r g a i d g n i m i t e e s ( 1 c b r d n a d e h c t e r t s s i 0 c b r d n a 1 c b r t n e r r u c e h t f o d o i r e p e h t , d e t c e t e d . y r a d n u o b d r o w e h t h t i w n g i l a o t table 5. S2061 transmitter pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 x t 6 x t 5 x t 4 x t 3 x t 2 x t 1 x t 0 x t l t ti 8 3 0 4 1 4 2 4 3 4 5 4 6 4 7 4 e h t n o n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a t a d t i m s n a r t . t s r i f d e t t i m s n a r t s i 0 x t . c b t f o e g d e g n i s i r c b tl t ti 7 2d e l l o r t n o c - l a t s y r c a , k c o l c e t y b t i m s n a r t d n a k c o l c e c n e r e f e r f o y c n e u q e r f e h t . r e i l p i t l u m k c o l c l l p e h t r o f k c o l c e c n e r e f e r . 0 1 y b d e d i v i d e t a r t i b e h t s i c b t n t s e t x tl t ti 9 3. t u p n i t s e t l a n r e t n i s e c a l p e r n t s e t x t , v 5 . 1 / v 0 d e l g g o t n e h w . n o i t a r e p o l a m r o n r o f h g i h e i t p x t n x t . f f i d l c e p o1 5 2 5 r e t t i m s n a r t l a i r e s e h t t u o d n e s t a h t s t u p t u o l c e p l a i t n e r e f f i d 5 7 e v i r d d n a a t a d w 0 5 r o w e h t s i p x t . v 2 C c c v o t n o i t a n i m r e t . t u p t u o e v i t a g e n e h t s i n x t d n a , t u p t u o e v i t i s o p 0 k t 1 k t l t t v li7 3 6 3 l a n o i t i d d a w o l l a s t u p n i e s e h t . h g i h e v i t c a . r e t c a r a h c k t i m s n a r t . r e d o c n e e h t y b d e t a r e n e g y l l a c i t a m o t u a e b o t s r e t c a r a h c k ) . 1 e l b a t e e s ( n e g kl t t v li3 3l e l l a r a p r o f ) k ( l o r t n o c r o ) d ( a t a d y f i c e p s o t d e s u . n e g r a h c k . 7 - 0 s t i b a t a d e m a r fl t t v li2 3e h t s l o r t n o c t u p n i e m a r f e h t , 0 s i n e g k f i . h g i h e v i t c a 5 . 8 2 k a , e v i t c a n e h w . s r e t c a r a h c 5 . 8 2 k r o a t a d f o n o i s s i m s n a r t e h t y b d e t a r e n e g e b l l i w y t i r a p s i d g n i n n u r t c e r r o c h t i w r e t c a r a h c n o t n e s e r p e t y b a t a d e h t , e v i t c a n i n e h w . r e d o c n e t i m s n a r t . y t i r a p s i d g n i n n u r t c e r r o c e h t h t i w d e d o c n e e b l l i w > 0 : 7 < n i a t a d k l c d r o wl t t v lo4 4o t y l s u o n o r h c n y s s e t a r e p o r e d o c n e e h t . r e d o c n e r o f k c o l c d r o w e t a r t i b e h t s i k l c d r o w e h t f o y c n e u q e r f e h t . k c o l c s i h t . 0 2 y b d e d i v i d table 6. S2061 receiver pin assignment and descriptions
7 serial backplane transceiver S2061 february 2, 1999 / revision c table 6. S2061 receiver pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d t e d c _ n el t ti5 2. n o i t c e t e d c n y s s e l b a n e , h g i h n e h w . t c e t e d a m m o c e l b a n e ) 9 - 0 ( x r , n r e t t a p c n y s r e t c a r a h c + a m m o c t i b - 7 e h t f o n o i t c e t e d e h t r o f y r a d n u o b d r o w e h t e l b a n e l l i w , ) x x x 1 1 1 1 1 0 0 : 5 . 8 2 k ( = . a t a d d e m a r f n u s a d e t a e r t s i a t a d , w o l n e h w . w o l l o f o t a t a d p x r n x r . f f i d l c e p v l i9 5 1 6 d e v i e c e r l c e p v l l a i t n e r e f f i d ) . d e l p u o c y l e v i t i c a p a c y l l a n r e t x e ( e h t s i n x r d n a , t u p n i e v i t i s o p e h t s i p x r . s t u p n i a t a d l a i r e s . d e s a i b y l l a n r e t n i . t u p n i e v i t a g e n p fl t to2 a t a h t s e t a c i d n i p f e v i t c a n e h w . h g i h e v i t c a . e s l u p e m a r f s i d n a d e t c e t e d n e e b s a h y t i r a p s i d r e h t i e f o r e t c a r a h c 5 . 8 2 k 7 e h t n o d e m r o f r e p s i t n e m n g i l a e t y b : e t o n . > 7 : 0 < x r n o t n e s e r p t o n , ) x x x 1 1 1 1 1 0 0 ( y t i r a p s i d e v i t a g e n h t i w r e t c a r a h c a m m o c t i b . 5 . 8 2 k l l u f e h t t e d k c o ll t t v lo4 6s a h r e v i e c e r e h t t a h t s e t a c i d n i . h g i h e v i t c a . t c e t e d k c o l . ) k c o l l l p ( n o i t a z i n o r h c n y s t i b d e v e i h c a g a l f kl t t v lo6 1e t y b a t a d d e d o c e d e h t s e t a c i d n i . h g i h e v i t c a . g a l f r e t c a r a h c k d e t a c i d n i s i n o i t a m r o f n i l o r t n o c . ) e t y b k ( r e t c a r a h c l a i c e p s a s i . a t a d s e t a c i d n i w o l a ; h g i h s i g a l f k r e v e n e h w r r e t y bl t t v lo1 e t y b d e v i e c e r e h t s e t a c i d n i . h g i h e v i t c a . g a l f r o r r e e t y b . r o r r e y t i r a p s i d r o r e t c a r a h c a d e n i a t n o c l t t d sl t t v li2 2c i g o l ( d e t c e n n o c n u s i l c e p d s n e h w h g i h e v i t c a . t c e t e d l a n g i s d e d n e - e l g n i s a . 1 c i g o l t a d l e h s i l c e p d s n e h w w o l e v i t c a . ) 0 e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e b o t t u p n i l t t v l s i l t t d s n e h w . r e w o p l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i o t a o t d e c r o f y l l a n r e t n i e b l l i w s n i p n / p x r e h t n o a t a d e h t , e v i t c a n i s n i p n / p x r e h t n o a t a d , e v i t c a s i l t t d s n e h w . o r e z t n a t s n o c . y l l a m r o n d e s s e c o r p e b l l i w l c e p d sl c e p v li1 2h g i h e v i t c a . n w o d - l l u p k 1 l a n r e t n i h t i w l c e p v l . t c e t e d l a n g i s l c e p v l k 0 1 d e d n e - e l g n i s a . 0 c i g o l t a d l e h s i l t t d s n e h w o t e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e b o t t u p n i s i l c e p d s n e h w . r e w o p l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i e b l l i w s n i p ) n / p x r ( n i a t a d l a i r e s e h t n o a t a d e h t , e v i t c a n i , e v i t c a s i l c e p d s n e h w . o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i n e h w . y l l a m r o n d e s s e c o r p e b l l i w s n i p n / p x r e h t n o a t a d d a e t s n i e l u d o m r e v i e c e r l a c i t p o e h t o t d e t c e n n o c e b o t s i l t t d s n a t n e m e l p m i o t h g i h d e i t e b d l u o h s l c e p d s n e h t , l c e p d s f o n a t n e m e l p m i o t d e t c e n n o c n u t f e l r o , t c e t e d l a n g i s w o l e v i t c a . t c e t e d l a n g i s h g i h e v i t c a 0 k r 1 k r l t t v lo4 1 5 1 e t a c i d n i s t u p t u o e s e h t . h g i h e v i t c a . r e t c a r a h c k e v i e c e r e e s ( . s r e t c a r a h c k 7 . 8 2 k d n a , 3 . 8 2 k , 1 . 8 2 k e h t f o n o i t p e c e r ) . 4 e l b a t
8 serial backplane transceiver S2061 february 2, 1999 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a r w el t ti 0 3l a i r e s r e t t i m s n a r t e h t s t c e l e s , h g i h n e h w . t u p n i p a r w e l b a n e p x r s t c e l e s , w o l n e h w . r e v i e c e r e h t o t d e t u o r e b o t a t a d t u p t u o p a r w e n e h w c i t a t s e r a n x t , p x t . ) n o i t a r e p o l a m r o n ( n x r d n a . h g i h s i t s rl t ti 3 2. t s e t y r o t c a f r o f p i h c e h t e z i l a i t i n i o t d e s u . w o l e v i t c a l e s e t a rl t ti 6 5. n o i t a r e p o l a m r o n r o f h g i h e i t . t s e t y r o t c a f r o f d e s u c c v l c e CC 9 2 6 2 3 5 8 5 v 3 . 3 + e r o c e e v l c e CC 4 2 8 2 5 3 8 4 7 5 d n u o r g e r o c d n g l t t3 7 1 d n u o r g l t t c c v l t t7 2 1 v 3 . 3 + l t t c c v o i l c e0 5v 3 . 3 + o / i l c e p e e v o i l c e5 5 9 4 d n u o r g o / i l c e p c c v a1 3 3 6 v 3 . 3 + g o l a n a e e v a4 3 2 6 d n u o r g g o l a n a c nCC0 2 4 5 0 6 n o i t c e n n o c o n table 5. S2061 common pin assignment and descriptions
9 serial backplane transceiver S2061 february 2, 1999 / revision c 1 2 3 4 5 6 7 8 9 10 11 19 20 21 22 23 24 25 26 27 28 29 62 61 60 59 58 57 56 55 54 53 52 48 47 46 45 44 43 42 41 40 39 38 S2061 37 36 eclvee tx0 tx1 tx2 wordclk tx3 tx4 tx5 tx6 txtestn tx7 tk0 tk1 35 34 33 eclvee avee kgen 17 18 rbc1 nc sdpecl sdttl rst eclvee en_cdet eclvcc tbc eclvee eclvcc ttlgnd rbc0 30 31 32 ewrap avcc frame 64 63 avee rxn nc rxp eclvcc eclvee ratesel ecliovee nc eclvcc txn lockdet avcc 51 50 49 txp ecliovcc ecliovee 12 13 byterr fp ttlgnd rx0 rx1 rx2 ttlvcc rx3 rx4 rx5 rx6 ttlvcc rx7 14 15 16 rk0 rk1 kflag figure 4. pin description and assignment
10 serial backplane transceiver S2061 february 2, 1999 / revision c figure 5. 64 pqfp/tep (14mm x 14mm) package thermal management device S2061 2.0w max 30?c/w power q ja 2.5?c/w q jc
11 serial backplane transceiver S2061 february 2, 1999 / revision c table 8. absolute maximum ratings table 9. recommended operating conditions table 10. reference clock requirements parameters description min max units conditions ft td 1 -2 t rcr , t rcf frequency tolerance symmetry refclk rise and fall time random jitter -100 40 +100 60 2 100 ppm % ns ps duty cycle at 50% pt. 20 ?80% peak-to-peak r e t e m a r a pn i mp y tx a mt i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? , c c v l c e , c c v l t t n o e g a t l o v o t t c e p s e r h t i w c c v a d n a , c c v o i l c e e e v / d n g 3 1 . 33 . 37 4 . 3v x t t p e c x e n i p t u p n i l t t n o e g a t l o v ] 7 : 0 [ 07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v c c v 0 . 2 - c c vv ] 7 : 0 [ x t a t a d l t t n o e g a t l o v00 . 5 r e t e m a r a pn i mp y tx a mt i n u s a i b r e d n u e r u t a r e p m e t e s a c5 5 -5 2 1c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j5 5 -0 5 1c ? e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w c c v n o e g a t l o v5 . 0 -0 . 7 +v t p e c x e n i p t u p n i l t t y n a n o e g a t l o v ] 7 : 0 [ x t 5 . 0 -7 4 . 3v ] 7 : 0 [ x t n i p t u p n i l t t n o e g a t l o v5 . 5 +v n i p t u p n i l c e p y n a n o e g a t l o v0c c vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m e c r u o s t u p t u o l c e p d e e p s h g i h t n e r r u c 0 5a m e g a t l o v e g r a h c s i d c i t a t s0 0 5v
12 serial backplane transceiver S2061 february 2, 1999 / revision c table 11. S2061 dc characteristics parameters description min typ units conditions v oh output high voltage (ttl) 2.5 vcc 2.0 gnd max v v cc = min, i oh = -400 a i cc supply current 485 577 ma outputs open, v cc = v cc max sq pattern p d 2.0 w outputs open, v cc = v cc max sq pattern v ol output low voltage (ttl) gnd .025 v v cc = max, i ol = 1 ma v ih v il i ih i il input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) 0.8 40 600 v v a a i h 1ma at v ih = 5.5v v in = 2.4v, v cc = max v in = 0.4v, v cc = max 600 serial output voltage swing input capacitance 1600 4 mv pf 50 to v cc -2.0v 100 1300 v diff d v out c in mv min. differential input voltage swing for differential pecl inputs 0.5 power dissipation 1.6 2.2
13 serial backplane transceiver S2061 february 2, 1999 / revision c parameters transmitter output jitter allocation description min max units conditions t 1 t 2 t sdr , t sdf data setup w.r.t. refclk data hold w.r.t. refclk serial data rise and fall 2 1.0 300 ns ns ps see note. 20% to 80%, tested on a sample basis. t j rms serial data output random jitter (rms) 20 ps rms, tested on a sample basis. measured with 1010 pattern. 80 ps peak-to-peak, tested on a sample basis. measured with k28.5 @ 1.25 ghz pattern. serial data output deterministic jitter (p-p) t dj table 13. S2061 transmitter timing table 14. S2061 receiver timing table 12. S2061 performance summary parameters description min max units conditions t 3 t 4 t 5 t 6 t 7 t rcr , t rcf t dr , t df t sdr , t sdf t lock duty cycle input jitter tolerance rbc0 to rbc1 skew data setup w.r.t. rbc0, rbc1 data hold w.r.t. rbc0, rbc1 data setup w.r.t. rbc0, rbc1 data hold w.r.t. rbc0, rbc1 rbc0, rbc1 rise and fall time data output rise and fall time serial data input rise and fall data acquisition lock time @ <1.0625gb/s rbc0/rbc1 duty cycle input data eye opening allocation at receiver input for ber 1e?2 3.0 1.5 2.5 1.5 40% 30% 1 3.0 3.0 300 2.4 60% ns ns ns ns ns ns ns ps s bit time tested on a sample basis. 1.0625 ghz mode 1.0625 ghz mode 1.250 ghz mode 1.250 ghz mode measured from .8v to 2.0v. measured from .8v to 2.0v. 20% to 80%. (see figure 10.) 8b/10b idle pattern sample basis as specified in fibre channel fc?h standard eye diagram jitter mask. r e t e m a r a p1 6 0 2 ss t i n us t i n u s t i n u s t i n us t i n u * y c n e u q e r f g n i t a r e p o 0 5 2 1 5 . 2 6 0 1s / t i b m d o i r e p k c o l c l a i r e s 0 0 8 . 1 4 9 .s n d o i r e p k c o l c e t y b 0 0 . 8 1 4 . 9s n e m i t n o i t i s i u q c a 0 5 2 0 5 2s n k c o l c e c n e r e f e r 0 . 5 2 1 5 2 . 6 0 1z h m h t d i w d r o w 0 1 0 1s t i b * 10% lock range, nominal frequency is per fc-ph standard. note: all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data level s (.8v or 2.0v). note: all ttl/cmos ac measurements are assumed to have the output load of 10pf.
14 serial backplane transceiver S2061 february 2, 1999 / revision c figure 6. transmitter timing diagram d0 246 13 57 t 1 t 2 serial data out tbc tx[0:7] 8 bit data figure 7. receiver timing diagram (1062.5 mbits/sec mode) d0 246 t 3 1357 t 5 t 4 k28.5 data t 5 t 4 tbc (106.25 mhz) rbc1 (53.125 mhz) rbc0 (53.125 mhz) 8 bit data and fp rx[0:7] serial data in figure 8. receiver timing diagram (1250 mbits/sec mode) d0 246 t 3 1357 t 7 t 6 k28.5 data t 7 t 6 tbc (125 mhz) rbc1 (62.5 mhz) rbc0 (62.5 mhz) 8 bit data and fp rx[0:7] serial data in
15 serial backplane transceiver S2061 february 2, 1999 / revision c t r t f 80% 50% 20% 80% 50% 20% figure 9. serial input rise and fall time acquisition time with the input eye diagram shown in figure 13, the S2061 will recover data with a 10 -9 ber within 50 bit times after an instantaneous phase shift of the in- coming data. figure 14. acquisition time eye diagram .10 0 -0.2 0.2 0.3 0.5 0.7 0.8 1.0 1.3 0 .30 .40 .60 .70 .90 1.0 normalized time normalized amplitude figure 10. serial output load figure 12. ttl input and output rise and fall time t r t f 2.0v .8v 2.0v .8v figure 13. receiver input eye diagram jitter mask amplitude bit time 30 % backplane 150 150 0.01 f 0.01 f figure 11. high speed differential inputs 0.01 f 0.01 f v cc - 0.65v 100
16 serial backplane transceiver S2061 february 2, 1999 / revision c ordering information x xxxx x prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (619) 450-9333 ? (800)755-2622 ? fax: (619) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s1 6 0 2m m 0 1 p f q p 4 6 C b

▲Up To Search▲

Price & Availability of S2061

	To Download S2061 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .